Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them

Just started writing SystemVerilog coming from a background of Verilog and C++ but the Verilog was a bit stale. There are a lot of things about SystemVerilog that seem counterintuitive from C++, such as automatic vs. static variables, that everything is essentially pointers, scoping rules, the way inheritance works. As I started reading the gotchas in this book, I realized I had already made several of them. I still make gotchas that I've read about but at least I recognize them.

Really an excellent tour of Verilog pitfalls. Overpriced, but you'll buy it anyway. :)

Verilog may appear to be "simple" for beginner because it is a loosely-typed language and its syntax is somewhat to that of C. In reality, Verilog is really a complex language and many intricate details and features are buried in the language standard (i.e., LRM, Language Reference Manual). Sometimes these details are counter-intuitive and cause unexpected behaviors (for example, the expressions "(a+b)>>1" and "(0+a+b)>>1" are likely to return different results). This book systematically lists and discusses these gotchas, provides guidelines to avoid these traps, and helps you to develop reliable and robust Verilog codes. It can save you many, many debugging hours down the road. Though somewhat expensive, this book is a valuable reference for serious Verilog developers. A simplified version of this book appears as a conference paper. You can search the web and take a look and decide whether it fits you need.